One or more aspects relate, in general, to processing within a computing environment, and in particular, to processing associated with memory being used to back address translation structures.
In computing environments that support virtualization technology, an operating system may be running on a virtual machine on a processor that supports multiple levels of address translation tables. In such an environment, the operating system is a guest of a hypervisor also executing in the computing environment.
When the memory backing an address translation table is paged-out to a storage medium, associated entries, such as translation look-aside buffer (TLB) entries that depend on those pages, may need to be purged. Further, when those entries are to be rebuilt, the latency for rebuilding those entries in such environments becomes much longer.
Further, since the hypervisor currently does not know what pages it owns that back address translation tables, it cannot be intelligent with its paging decisions. Although there are existing mechanisms for an operating system to inform the hypervisor of the likelihood of a page being reused, this is often just a suggestion and may take a lot of work by the operating system to determine how often a page is being used.